Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ___.
GATE 2014 · Computer Organization and Architecture · Pipelining · medium
Answer: Speedup = 6 / (1 + 0.25*2) = 6 / 1.5 = 4.0
- Average stall cycles per instruction: avg_stall = 0.25 * 2 = 0.5 cycles per instruction
- Average CPI of pipelined processor: CPI_pipeline = 1 + 0.5 = 1.5
- Speedup calculation: For a non-pipelined processor, CPI = n = 6 (all 6 stages run sequentially). Speedup = 6 / 1.5 = 4.0
- Verify using instruction count approach: For N instructions: Non-pipeline time = N * 6 * T (executes all 6 stages sequentially per instruction) Pipeline stall cycles = 0.25 * N * 2 = 0.5N extra cycles Pipeline time (large N) = (N + 0.5N) * T = 1.5N * T Speedup = (6N * T) / (1.5N * T) = 6 / 1.5 = 4.0