A 5-stage pipelined processor has stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform O...

Question

A 5-stage pipelined processor has stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO), and Write Operand (WO). The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

Instruction        Meaning of Instruction
t1: MUL R1,R2,R3   R1 = R2 * R3
t2: DIV R1,R4,R1   R1 = R4 / R1
t3: ADD R5,R6,R1   R5 = R6 + R1
t4: SUB R5,R5,R7   R5 = R5 - R7

A. 13
B. 15
C. 17
D. 19

Accepted Answer

Total clock cycles = 19. Answer: D. 19 We have a 5-stage pipeline where the PO (execution) stage takes varying cycles depending on the instruction type. Instructions depend on each other (data hazards): t2 reads R1 written by t1, t3 reads R1 written by t2, t4 reads R5 written by t3. Operand forwarding allows the result to be used as soon as PO completes (without waiting for WO), but stalls are still needed if the consumer's OF stage would happen before the producer's PO stage ends.