The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_15 to A_0. The chip select (CS) logic uses a NAND gate whose inputs are A_15, NOT(A_14), A_13, NOT(A_12) and an AND gate with A_11, NOT(A_10). The CS is active low. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? A. C800 to CFFF B. CA00 to CAFF C. C800 to C8FF D. DA00 to DFFF

GATE 2019 · Computer Organization and Architecture · Memory Interfacing · medium

Answer: B. CA00 to CAFF

1. Determine fixed address bit values for CS assertion: From the chip select logic: A_15=1, NOT(A_14) goes to NAND so A_14=0, A_13=1, NOT(A_12) so A_12=0, AND gate inputs: A_11=1, NOT(A_10) so A_10=0. Fixed bits: A_15=1, A_14=0, A_13=1, A_12=0, A_11=1, A_10=0
2. Form the binary address prefix: Fixed: 1 1 0 0 | 1 0 1 0 | free (A_7..A_0). In hex: 1100 = C, 1010 = A, so prefix = CA. Free bits A_7..A_0 range from 00 to FF.
3. Verify the address range: Start address: CA00 (hex) = 1100 1010 0000 0000. End address: CAFF (hex) = 1100 1010 1111 1111. This is a 256-byte range enabled by CS. This matches option B.