Consider the following data path of a simple non-pipelined CPU. The registers A, B, the ALU, and the MUX are 8-bit wide. PC and SP are 16-bit registers. The MUX is of size 8x1 and the memory is of size 2^16 x 8. Each memory operation takes 2 clock cycles and uses MAR (Memory Address Register) and MDR (Memory Data Register). SP can be decremented locally. The CPU instruction 'push r' where r = A or B has the specification: M[SP] <- r SP <- SP - 1 How many CPU clock cycles are required to execute the 'push r' instruction? A. 2 B. 3 C. 4 D. 5

GATE 2001 · Computer Organization and Architecture · Data Path · medium

Answer: C. 4

  1. Cycle 1: Set up memory address: The current value of SP is placed on the data bus and loaded into MAR. This establishes the target address for the memory write. Cost: 1 cycle.
  2. Cycle 2: Set up data and start memory write: Register r (A or B, 8-bit) is placed on the bus and loaded into MDR. The memory write operation begins in this cycle. Cost: 1 cycle.
  3. Cycle 3: Complete memory write: The memory write operation completes (2nd of 2 memory cycles). M[SP_old] now holds the value of r. Cost: 1 cycle.
  4. Cycle 4: Decrement SP locally: Because SP can be decremented locally (without using the ALU and internal bus), this operation completes in exactly 1 clock cycle. SP now points to the new top of stack. Cost: 1 cycle.
  5. Total clock cycles: Cycle 1: MAR <- SP. Cycle 2: MDR <- r (start mem write). Cycle 3: Mem write done. Cycle 4: SP <- SP - 1 (local). Total = 4 clock cycles.