Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on...

Question

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ________.

Accepted Answer

The miss rate of L2 is 0.05. There are two levels of cache (L1 and L2). The CPU generates 1.4 memory accesses per instruction on average. L1 misses 10% of the time. Among those references that actually reach L2, we need to find what fraction L2 also misses. We are told L2 sees 7 misses per 1000 instructions total.