If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? A. Width of tag comparator B. Width of set index decoder C. Width of way-select multiplexer D. Number of cache blocks

GATE 2014 · Computer Organization and Architecture · Cache Memory · medium

Answer: D. Number of cache blocks

1. Determine changes when associativity doubles: Let original: associativity = k, sets = S, total blocks = S*k. After doubling: associativity = 2k, sets = S/2, total blocks = (S/2)*(2k) = S*k. Index bits change: was log2(S), now log2(S/2) = log2(S) - 1. Tag bits increase by 1. Way-select MUX doubles in width.
2. Evaluate each option: A. Tag comparator width: tag bits increase by 1 (index decreased) => AFFECTED. B. Set index decoder width: one fewer index bit needed => AFFECTED. C. Way-select MUX width: ways doubled (k to 2k) => MUX must select among 2x lines => AFFECTED. D. Number of cache blocks = capacity / block_size = unchanged (both held constant) => NOT AFFECTED.