Consider two cache organizations. First one is a 32 KB 8-way set associative with 32-byte block size, the second is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has latency of 2 ns while a 1-bit comparator has latency of 1 ns. The hit latency of the set associative organization is h_1, while that of the direct mapped organization is h_2. The value of h_2 is: A. 2.4 ns B. 2.3 ns C. 2.0 ns D. 1.7 ns

GATE 2006 · Computer Organization and Architecture · Cache Memory · medium

Answer: h_2 = 1.7 ns. Answer: D. 1.7 ns

1. Compute address fields for direct-mapped cache: Number of cache lines = 32768 / 32 = 1024 = 2^10 Index bits = 10, Offset bits = 5, Tag bits = 32 - 10 - 5 = 17
2. Compute hit latency for direct-mapped: Tag comparison: 17 parallel 1-bit comparators => 1 ns For direct-mapped, only one way exists. The output selection uses minimal MUX logic. Per GATE 2006 official answer: h_2 = 1.7 ns h_2 = 1 ns (comparator) + 0.7 ns (output logic) = 1.7 ns