Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed. True/False. Explain.
GATE 1990 · Computer Organization and Architecture · Cache Memory · medium
Answer: TRUE — Block transfers cause the cache controller to issue a burst of consecutive-address requests that map to successive interleaved banks, keeping all banks busy and allowing the interleaved main memory to operate at its maximum (pipelined) throughput.
- How interleaved memory achieves peak bandwidth: In a k-way interleaved memory, consecutive address words reside in banks 0, 1, ..., k-1 cyclically. A memory controller can issue a new read to bank i while bank i-1 is still completing its access. After an initial latency of one full memory cycle (t_m), one new word arrives every t_m/k time units — the maximum possible rate.
- Why block transfer enables this maximum speed: When the cache controller requests a full block (say 8 words starting at address A), it issues reads to addresses A, A+1, A+2, ... in rapid succession. These addresses map to successive banks, so the interleaved memory can pipeline all of them. The entire block is delivered at near-maximum memory bandwidth. If only one word at a time were fetched (non-block), the interleave advantage would be lost for each separate access.